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				<h2>5.3 Verilog 时钟分频</h2>				<h3><em>分类</em> <a href="../w3cnote_genre/verilog2" title="Verilog 教程高级篇" >Verilog 教程高级篇</a> </h3>
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					<h3>关键词：偶数分频，奇数分频，半整数分频，小数分频</h3>
<p>初学 Verilog 时许多模块都是由计数器与分频器组成的，例如 PWM 脉宽调制、频率计等。分频逻辑也往往通过计数逻辑完成。本节主要对偶数分频、奇数分频、半整数分频以及小数分频进行简单的总结。</p>
<h3>
偶数分频</h3>
<p>采用触发器反向输出端连接到输入端的方式，可构成简单的 2 分频电路。</p><p>
以此为基础进行级联，可构成 4 分频，8 分频电路。</p><p>
电路实现如下图所示，用 Verilog 描述时只需使用简单的取反逻辑即可。</p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/v-division-1.png"></p>
<p>如果偶数分频系数过大，就需要对分频系数 N 循环计数进行分频。在计数周期达到分频系数中间数值 N/2 时进行时钟翻转，可保证分频后时钟的占空比为 50%。因为是偶数分频，也可以对分频系数中间数值 N/2 进行循环计数。</p><p>
偶数分频的 Verilog 描述举例如下。</p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">module</span> even_divisor<br />
&nbsp; <span style="color: #5D478B;">#</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">parameter</span> DIV_CLK <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">10</span> <span style="color: #9F79EE;">&#41;</span><br />
&nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; rstn <span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; clk<span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">output</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_div2<span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">output</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_div4<span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">output</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_div10<br />
&nbsp; &nbsp; <span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//2 分频</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_div2_r <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk <span style="color: #A52A2A; font-weight: bold;">or</span> <span style="color: #A52A2A; font-weight: bold;">negedge</span> rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">!</span>rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_div2_r &nbsp; &nbsp; <span style="color: #5D478B;">&lt;=</span> 'b0 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_div2_r &nbsp; &nbsp; <span style="color: #5D478B;">&lt;=</span> <span style="color: #5D478B;">~</span>clk_div2_r <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">assign</span> &nbsp; &nbsp; &nbsp; clk_div2 <span style="color: #5D478B;">=</span> clk_div2_r <span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//4 分频</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_div4_r <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk_div2 <span style="color: #A52A2A; font-weight: bold;">or</span> <span style="color: #A52A2A; font-weight: bold;">negedge</span> rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">!</span>rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_div4_r &nbsp; &nbsp; <span style="color: #5D478B;">&lt;=</span> 'b0 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_div4_r &nbsp; &nbsp; <span style="color: #5D478B;">&lt;=</span> <span style="color: #5D478B;">~</span>clk_div4_r <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">assign</span> clk_div4 &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">=</span> clk_div4_r <span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//N/2 计数</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;cnt <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk <span style="color: #A52A2A; font-weight: bold;">or</span> <span style="color: #A52A2A; font-weight: bold;">negedge</span> rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">!</span>rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;cnt &nbsp; &nbsp;<span style="color: #5D478B;">&lt;=</span> 'b0 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>cnt <span style="color: #5D478B;">==</span> <span style="color: #9F79EE;">&#40;</span>DIV_CLK<span style="color: #5D478B;">/</span><span style="color: #ff0055;">2</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">-</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;cnt &nbsp; &nbsp;<span style="color: #5D478B;">&lt;=</span> 'b0 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;cnt &nbsp; &nbsp;<span style="color: #5D478B;">&lt;=</span> cnt <span style="color: #5D478B;">+</span> <span style="color: #ff0055;">1'b1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//输出时钟</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_div10_r <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk <span style="color: #A52A2A; font-weight: bold;">or</span> <span style="color: #A52A2A; font-weight: bold;">negedge</span> rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">!</span>rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_div10_r <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>cnt <span style="color: #5D478B;">==</span> <span style="color: #9F79EE;">&#40;</span>DIV_CLK<span style="color: #5D478B;">/</span><span style="color: #ff0055;">2</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">-</span><span style="color: #ff0055;">1</span> <span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_div10_r <span style="color: #5D478B;">&lt;=</span> <span style="color: #5D478B;">~</span>clk_div10_r <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">assign</span> clk_div10 <span style="color: #5D478B;">=</span> clk_div10_r <span style="color: #5D478B;">;</span><br />
<span style="color: #A52A2A; font-weight: bold;">endmodule</span><br />
</div></div><p>
testbench 中只需给入激励时钟等信号即可，这里不再列出。</p><p>
仿真结果如下。</p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/v-division-2.png"></p>
<h3>奇数分频</h3><p>
奇数分频如果不要求占空比为 50%，可按照偶数分频的方法进行分频。即计数器对分频系数 N 进行循环计算，然后根据计数值选择一定的占空比输出分频时钟。</p><p>
如果奇数分频输出时钟的高低电平只差一个 cycle ，则可以利用源时钟双边沿特性并采用"与操作"或"或操作"的方式将分频时钟占空比调整到 50%。</p>
<p><strong>或操作调整占空比</strong></p><p>
采用"或操作"产生占空比为 50% 的 3 分频时序图如下所示。</p><p>
利用源时钟上升沿分频出高电平为 1 个 cycle、低电平为 2 个 cycle 的 3 分频时钟。</p><p>
利用源时钟下降沿分频出高电平为 1 个 cycle、低电平为 2 个 cycle 的 3 分拼时钟。</p><p>
两个 3 分频时钟应该在计数器相同数值、不同边沿下产生，相位差为半个时钟周期。然后将 2 个时钟进行"或操作"，便可以得到占空比为 50% 的 3 分频时钟。</p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/v-division-3.png"></p>

<p>同理，9 分频时，则需要在上升沿和下降沿分别产生 4 个高电平、5 个低电平的 9 分频时钟，然后再对两个时钟做"或操作"即可。Verilog 描述如下。</p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">module</span> odo_div_or<br />
&nbsp; <span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">parameter</span> DIV_CLK <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">9</span><span style="color: #9F79EE;">&#41;</span><br />
&nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; rstn <span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; clk<span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">output</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_div9<br />
&nbsp; &nbsp; <span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//计数器</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;cnt <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk <span style="color: #A52A2A; font-weight: bold;">or</span> <span style="color: #A52A2A; font-weight: bold;">negedge</span> rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">!</span>rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;cnt &nbsp; &nbsp;<span style="color: #5D478B;">&lt;=</span> 'b0 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>cnt <span style="color: #5D478B;">==</span> DIV_CLK<span style="color: #5D478B;">-</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;cnt &nbsp; &nbsp;<span style="color: #5D478B;">&lt;=</span> 'b0 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;cnt &nbsp; &nbsp;<span style="color: #5D478B;">&lt;=</span> cnt <span style="color: #5D478B;">+</span> <span style="color: #ff0055;">1'b1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//在上升沿产生9分频</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clkp_div9_r <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk <span style="color: #A52A2A; font-weight: bold;">or</span> <span style="color: #A52A2A; font-weight: bold;">negedge</span> rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">!</span>rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clkp_div9_r <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>cnt <span style="color: #5D478B;">==</span> <span style="color: #9F79EE;">&#40;</span>DIV_CLK<span style="color: #5D478B;">&gt;&gt;</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">-</span><span style="color: #ff0055;">1</span> <span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span> <span style="color: #00008B; font-style: italic;">//计数4-8位低电平</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; clkp_div9_r <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>cnt <span style="color: #5D478B;">==</span> DIV_CLK<span style="color: #5D478B;">-</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span> <span style="color: #00008B; font-style: italic;">//计数 0-3 为高电平</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; clkp_div9_r <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; <br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//在下降沿产生9分频</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clkn_div9_r <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">negedge</span> clk <span style="color: #A52A2A; font-weight: bold;">or</span> <span style="color: #A52A2A; font-weight: bold;">negedge</span> rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">!</span>rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clkn_div9_r <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>cnt <span style="color: #5D478B;">==</span> <span style="color: #9F79EE;">&#40;</span>DIV_CLK<span style="color: #5D478B;">&gt;&gt;</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">-</span><span style="color: #ff0055;">1</span> <span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span> <br />
&nbsp; &nbsp; &nbsp; &nbsp; clkn_div9_r <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>cnt <span style="color: #5D478B;">==</span> DIV_CLK<span style="color: #5D478B;">-</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span> <br />
&nbsp; &nbsp; &nbsp; &nbsp; clkn_div9_r <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//或操作，往往使用基本逻辑单元库</span><br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">// or (clk_div9, clkp_div9_r, clkn_div9_r) ;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">assign</span> clk_div9 <span style="color: #5D478B;">=</span> clkp_div9_r <span style="color: #5D478B;">|</span> clkn_div9_r <span style="color: #5D478B;">;</span><br />
<br />
<span style="color: #A52A2A; font-weight: bold;">endmodule</span><br />
</div></div><p>
仿真结果如下。</p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/v-division-4.png"></p>
<p><strong>与操作调整占空比</strong></p><p>
采用"与操作"产生占空比为 50% 的 3 分频时序图如下所示。</p><p>
利用源时钟上升沿分频出高电平为 2 个 cycle、低电平为 1 个 cycle 的 3 分频时钟。</p><p>
利用源时钟下降沿分频出高电平为 2 个 cycle、低电平为 1 个 cycle 的 3 分拼时钟。</p><p>
两个 3 分频时钟应该在计数器相同数值、不同边沿下产生，相位差为半个时钟周期。然后将 2 个时钟进行"与操作"，便可以得到占空比为 50% 的 3 分频时钟。</p>

<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/v-division-5.png"></p><p>
同理，9 分频时，则需要在上升沿和下降沿分别产生 5 个高电平、4 个低电平的 9 分频时钟，然后再对两个时钟做"与操作"即可。Verilog 描述如下。</p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">module</span> odo_div_and<br />
&nbsp; &nbsp;<span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span> <span style="color: #A52A2A; font-weight: bold;">parameter</span> DIV_CLK <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">9</span> <span style="color: #9F79EE;">&#41;</span><br />
&nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; rstn <span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; clk<span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">output</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_div9<br />
&nbsp; &nbsp; <span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//计数器</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;cnt <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk <span style="color: #A52A2A; font-weight: bold;">or</span> <span style="color: #A52A2A; font-weight: bold;">negedge</span> rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">!</span>rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;cnt &nbsp; &nbsp;<span style="color: #5D478B;">&lt;=</span> 'b0 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>cnt <span style="color: #5D478B;">==</span> DIV_CLK<span style="color: #5D478B;">-</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;cnt &nbsp; &nbsp;<span style="color: #5D478B;">&lt;=</span> 'b0 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;cnt &nbsp; &nbsp;<span style="color: #5D478B;">&lt;=</span> cnt <span style="color: #5D478B;">+</span> <span style="color: #ff0055;">1'b1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//在上升沿产生9分频</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clkp_div9_r <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk <span style="color: #A52A2A; font-weight: bold;">or</span> <span style="color: #A52A2A; font-weight: bold;">negedge</span> rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">!</span>rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clkp_div9_r <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>cnt <span style="color: #5D478B;">==</span> <span style="color: #9F79EE;">&#40;</span>DIV_CLK<span style="color: #5D478B;">&gt;&gt;</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span> <span style="color: #00008B; font-style: italic;">//计数5-8位低电平</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; clkp_div9_r <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>cnt <span style="color: #5D478B;">==</span> DIV_CLK<span style="color: #5D478B;">-</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span> <span style="color: #00008B; font-style: italic;">//计数 0-4 为高电平</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; clkp_div9_r <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//在下降沿产生9分频</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clkn_div9_r <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">negedge</span> clk <span style="color: #A52A2A; font-weight: bold;">or</span> <span style="color: #A52A2A; font-weight: bold;">negedge</span> rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">!</span>rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clkn_div9_r <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>cnt <span style="color: #5D478B;">==</span> <span style="color: #9F79EE;">&#40;</span>DIV_CLK<span style="color: #5D478B;">&gt;&gt;</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span> <br />
&nbsp; &nbsp; &nbsp; &nbsp; clkn_div9_r <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>cnt <span style="color: #5D478B;">==</span> DIV_CLK<span style="color: #5D478B;">-</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span> <br />
&nbsp; &nbsp; &nbsp; &nbsp; clkn_div9_r <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//与操作，往往使用基本逻辑单元库</span><br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//and (clk_div9, clkp_div9_r, clkn_div9_r) ;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">assign</span> clk_div9 <span style="color: #5D478B;">=</span> clkp_div9_r <span style="color: #5D478B;">&amp;</span> clkn_div9_r <span style="color: #5D478B;">;</span><br />
<br />
<span style="color: #A52A2A; font-weight: bold;">endmodule</span><br />
</div></div><p>
仿真结果如下。</p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/v-division-6.png"></p>
<h3>
半整数分频</h3><p>
利用时钟的双边沿逻辑，可以对时钟进行半整数的分频。但是无论怎么调整，半整数分频的占空比不可能是 50%。半整数分频的方法有很多，这里只介绍一种和奇数分频调整占空比类似的方法。</p>
<ul><li>
(1) 例如进行 3.5 倍分频时，计数器循环计数到 7，分别产生由 4 个和 3 个源时钟周期组成的 2 个分频时钟。从 7 个源时钟产生了 2 个分频时钟的角度来看，该过程完成了 3.5 倍的分频，但是每个分频时钟并不是严格的 3.5 倍分频。</li><li>
(2) 下面对周期不均匀的分频时钟进行调整。一次循环计数中，在源时钟下降沿分别产生由 4 个和 3 个源时钟周期组成的 2 个分频时钟。相对于第一次产生的 2 个周期不均匀的时钟，本次产生的 2 个时钟相位一个延迟半个源时钟周期，一个提前半个源时钟周期。</li><li>
(3) 将两次产生的时钟进行"或操作"，便可以得到周期均匀的 3.5 倍分频时钟。分频波形示意图如下所示。</li></ul>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/v-division-7.png"></p>
<p>3.5 倍时钟分频的 Verilog 描述如下。</p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">module</span> half_divisor<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; rstn <span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; clk<span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">output</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_div3p5<br />
&nbsp; &nbsp; <span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//计数器</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">parameter</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;MUL2_DIV_CLK <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">7</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;cnt <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk <span style="color: #A52A2A; font-weight: bold;">or</span> <span style="color: #A52A2A; font-weight: bold;">negedge</span> rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">!</span>rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;cnt &nbsp; &nbsp;<span style="color: #5D478B;">&lt;=</span> 'b0 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>cnt <span style="color: #5D478B;">==</span> MUL2_DIV_CLK<span style="color: #5D478B;">-</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span> <span style="color: #00008B; font-style: italic;">//计数2倍分频比</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;cnt &nbsp; &nbsp;<span style="color: #5D478B;">&lt;=</span> 'b0 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;cnt &nbsp; &nbsp;<span style="color: #5D478B;">&lt;=</span> cnt <span style="color: #5D478B;">+</span> <span style="color: #ff0055;">1'b1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_ave_r <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk <span style="color: #A52A2A; font-weight: bold;">or</span> <span style="color: #A52A2A; font-weight: bold;">negedge</span> rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">!</span>rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_ave_r <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//first cycle: 4 source clk cycle</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>cnt <span style="color: #5D478B;">==</span> <span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_ave_r <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//2nd cycle: 3 source clk cycle</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>cnt <span style="color: #5D478B;">==</span> <span style="color: #9F79EE;">&#40;</span>MUL2_DIV_CLK<span style="color: #5D478B;">/</span><span style="color: #ff0055;">2</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">+</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_ave_r <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_ave_r <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//adjust</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_adjust_r <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">negedge</span> clk <span style="color: #A52A2A; font-weight: bold;">or</span> <span style="color: #A52A2A; font-weight: bold;">negedge</span> rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">!</span>rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_adjust_r <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//本次时钟只为调整一致的占空比</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>cnt <span style="color: #5D478B;">==</span> <span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_adjust_r <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//本次时钟只为调整一致的精确分频比</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>cnt <span style="color: #5D478B;">==</span> <span style="color: #9F79EE;">&#40;</span>MUL2_DIV_CLK<span style="color: #5D478B;">/</span><span style="color: #ff0055;">2</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">+</span><span style="color: #ff0055;">1</span> <span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_adjust_r <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_adjust_r <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">assign</span> clk_div3p5 <span style="color: #5D478B;">=</span> clk_adjust_r <span style="color: #5D478B;">|</span> clk_ave_r <span style="color: #5D478B;">;</span><br />
<br />
<span style="color: #A52A2A; font-weight: bold;">endmodule</span><br />
</div></div><p>
仿真结果如下。</p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/v-division-8.png"></p>

<h3>小数分频</h3>
<p><strong>基本原理</strong></p><p>
不规整的小数分频不能做到分频后的每个时钟周期都是源时钟周期的小数分频倍，更不能做到分频后的时钟占空比均为 50%，因为 Verilog 不能对时钟进行小数计数。和半整数分频中第一次分频时引入的"平均频率"概念类似，小数分频也是基于可变分频和多次平均的方法实现的。</p><p>

例如进行 7.6 倍分频，则保证源时钟 76 个周期的时间等于分频时钟 10 个周期的时间即可。此时需要在 76 个源时钟周期内进行 6 次 8 分频，4 次 7 分频。再例如进行 5.76 分频，需要在 576 个源时钟周期内进行 76 次 6 分频，24 次 5 分频。</p>
<p>
下面阐述下这些分频参数的计算过程。</p><p>
当进行 7 分频时，可以理解为 70 个源时钟周期内进行 10 次 7 分频。在 76 个源时钟周期内仍然进行 10 次分频，相当于将多余的 6 个源时钟周期增加、分配到 70 个源时钟周期内，即完成了 7.6 倍分频操作。分频过程中必然有 6 个分频时钟是 8 分频得到的，剩下的 4 个分频时钟则仍然会保持原有的 7 分频状态。</p>
<p>
很多地方给出了计算这些分频参数的两元一次方程组，如下所示。其原理和上述分析一致，建议掌握上述计算过程。</p>
<pre>7N + 8M = 76
N  + M   = 10 </pre><p>
其中 7 为整数分频，N 整数分频的次数；8 与 M 为整数分频加一后的分频系数及其分频次数。</p>
<p><strong>平均原理</strong></p><p>
以 7.6 倍分频为例，7 分频和 8 分频的实现顺序一般有以下 4 种：</p><ul><li>
(1)  先进行 4 次 7 分频，再进行 6 次 8 分频；</li><li>
(2)  先进行 6 次 8 分频，再进行 4 次 7 分频；</li><li>
(3)  将 4 次 7 分频平均的插入到 6 次 8 分频中；</li><li>
(4)  将 6 次 8 分频平均的插入到 4 次 7 分频中。</li></ul><p>
前两种方法时钟频率不均匀，相位抖动较大，所以一般会采用后两种平均插入的方法进行小数分频操作。</p>
<p>
平均插入可以通过分频次数差累计的方法实现，7.6 分频的实现过程如下：</p><ul><li>
(1) 第一次分频次数差值为 76-10*7 = 6 < 10，第一次进行 7 分频。</li><li>
(2) 第二次差值累加结果为 6+6=12 > 10，第二次使用 8 分频，同时差值修改为 12-10=2。</li><li>
(3) 第三次差值累加结果为 2+6=8 < 10，第三次使用 7 分频。</li><li>
(4) 第四次差值累加结果为 8+6=14 > 10，第四次使用 8 分频，差值修改为 14-10=4。</li></ul>
<p>以此类推，完成将 6 次 8 分频平均插入到 4 次 7 分频的过程。</p>
<p>
下表展示了平均插入法的分频过程。</p>
<table class="reference"><thead><tr><th style="text-align:center;"><span>分频次数</span></th><th style="text-align:left;"><span>差值累加</span></th><th style="text-align:center;"><span>差值修改</span></th><th style="text-align:left;"><span>分频周期</span></th></tr></thead><tbody><tr><td style="text-align:center;"><span>1</span></td><td style="text-align:left;"><span>6</span></td><td style="text-align:center;"><span>6</span></td><td style="text-align:left;"><span>7</span></td></tr><tr><td style="text-align:center;"><span>2</span></td><td style="text-align:left;"><span>6+6=12</span></td><td style="text-align:center;"><span>2</span></td><td style="text-align:left;"><span>8</span></td></tr><tr><td style="text-align:center;"><span>3</span></td><td style="text-align:left;"><span>2+6=8</span></td><td style="text-align:center;"><span>8</span></td><td style="text-align:left;"><span>7</span></td></tr><tr><td style="text-align:center;"><span>4</span></td><td style="text-align:left;"><span>8+6=14</span></td><td style="text-align:center;"><span>4</span></td><td style="text-align:left;"><span>8</span></td></tr><tr><td style="text-align:center;"><span>5</span></td><td style="text-align:left;"><span>4+6=10</span></td><td style="text-align:center;"><span>0</span></td><td style="text-align:left;"><span>8</span></td></tr><tr><td style="text-align:center;"><span>6</span></td><td style="text-align:left;"><span>6</span></td><td style="text-align:center;"><span>6</span></td><td style="text-align:left;"><span>7</span></td></tr><tr><td style="text-align:center;"><span>7</span></td><td style="text-align:left;"><span>6+6=12</span></td><td style="text-align:center;"><span>2</span></td><td style="text-align:left;"><span>8</span></td></tr><tr><td style="text-align:center;"><span>8</span></td><td style="text-align:left;"><span>2+6=8</span></td><td style="text-align:center;"><span>8</span></td><td style="text-align:left;"><span>7</span></td></tr><tr><td style="text-align:center;"><span>9</span></td><td style="text-align:left;"><span>8+6=14</span></td><td style="text-align:center;"><span>4</span></td><td style="text-align:left;"><span>8</span></td></tr><tr><td style="text-align:center;"><span>10</span></td><td style="text-align:left;"><span>4+6=10</span></td><td style="text-align:center;"><span>0</span></td><td style="text-align:left;"><span>8</span></td></tr></tbody></table>
<p><strong>设计仿真</strong></p><p>
基于上述小数分频实现方法的 Verilog 描述如下。</p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">module</span> frac_divisor<br />
&nbsp; <span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">parameter</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;SOURCE_NUM <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">76</span> <span style="color: #5D478B;">,</span> <span style="color: #00008B; font-style: italic;">//cycles in source clock</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">parameter</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;DEST_NUM &nbsp; <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">10</span> &nbsp;<span style="color: #00008B; font-style: italic;">//cycles in destination clock</span><br />
&nbsp; &nbsp;<span style="color: #9F79EE;">&#41;</span><br />
&nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; rstn <span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; clk<span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">output</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_frac<br />
&nbsp; &nbsp; <span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; <br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//7分频参数、8分频参数、次数差值</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">parameter</span> &nbsp; &nbsp;SOURCE_DIV <span style="color: #5D478B;">=</span> SOURCE_NUM<span style="color: #5D478B;">/</span>DEST_NUM <span style="color: #5D478B;">;</span> <br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">parameter</span> &nbsp; &nbsp;DEST_DIV &nbsp; <span style="color: #5D478B;">=</span> SOURCE_DIV <span style="color: #5D478B;">+</span> <span style="color: #ff0055;">1</span><span style="color: #5D478B;">;</span> <br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">parameter</span> &nbsp; &nbsp;DIFF_ACC &nbsp; <span style="color: #5D478B;">=</span> SOURCE_NUM <span style="color: #5D478B;">-</span> SOURCE_DIV<span style="color: #5D478B;">*</span>DEST_NUM <span style="color: #5D478B;">;</span><br />
<br />
<br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;cnt_end_r <span style="color: #5D478B;">;</span> &nbsp;<span style="color: #00008B; font-style: italic;">//可变分频周期</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;main_cnt <span style="color: #5D478B;">;</span> &nbsp; <span style="color: #00008B; font-style: italic;">//主计数器</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_frac_r <span style="color: #5D478B;">;</span> <span style="color: #00008B; font-style: italic;">//时钟输出，高电平周期数为1</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk <span style="color: #A52A2A; font-weight: bold;">or</span> <span style="color: #A52A2A; font-weight: bold;">negedge</span> rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">!</span>rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;main_cnt &nbsp; &nbsp;<span style="color: #5D478B;">&lt;=</span> 'b0 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_frac_r &nbsp;<span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>main_cnt <span style="color: #5D478B;">==</span> cnt_end_r<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;main_cnt &nbsp; &nbsp;<span style="color: #5D478B;">&lt;=</span> 'b0 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_frac_r &nbsp;<span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">1'b1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;main_cnt &nbsp; &nbsp;<span style="color: #5D478B;">&lt;=</span> main_cnt <span style="color: #5D478B;">+</span> <span style="color: #ff0055;">1'b1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk_frac_r &nbsp;<span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//输出时钟</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">assign</span> &nbsp; &nbsp; &nbsp; clk_frac &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">=</span> clk_frac_r <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//差值累加器使能控制</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> &nbsp; &nbsp; &nbsp; &nbsp; diff_cnt_en &nbsp; &nbsp; <span style="color: #5D478B;">=</span> main_cnt <span style="color: #5D478B;">==</span> cnt_end_r <span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//差值累加器逻辑</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">4</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;diff_cnt_r <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">4</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; diff_cnt <span style="color: #5D478B;">=</span> diff_cnt_r <span style="color: #5D478B;">&gt;=</span> DEST_NUM <span style="color: #5D478B;">?</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;diff_cnt_r <span style="color: #5D478B;">-</span><span style="color: #ff0055;">10</span> <span style="color: #5D478B;">+</span> DIFF_ACC <span style="color: #5D478B;">:</span> <br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;diff_cnt_r <span style="color: #5D478B;">+</span> DIFF_ACC <span style="color: #5D478B;">;</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;<br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk <span style="color: #A52A2A; font-weight: bold;">or</span> <span style="color: #A52A2A; font-weight: bold;">negedge</span> rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">!</span>rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;diff_cnt_r <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>diff_cnt_en<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;diff_cnt_r <span style="color: #5D478B;">&lt;=</span> diff_cnt <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//分频周期变量的控制逻辑</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk <span style="color: #A52A2A; font-weight: bold;">or</span> <span style="color: #A52A2A; font-weight: bold;">negedge</span> rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">!</span>rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;cnt_end_r &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">&lt;=</span> SOURCE_DIV<span style="color: #5D478B;">-</span><span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//差值累加器溢出时，修改分频周期</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>diff_cnt <span style="color: #5D478B;">&gt;=</span> <span style="color: #ff0055;">10</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;cnt_end_r &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">&lt;=</span> DEST_DIV<span style="color: #5D478B;">-</span><span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;cnt_end_r &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">&lt;=</span> SOURCE_DIV<span style="color: #5D478B;">-</span><span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
<span style="color: #A52A2A; font-weight: bold;">endmodule</span><br />
</div></div>
<p>仿真结果如下。</p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/v-division-9.png"></p>


<h3>分频小结</h3><p>
偶数分频不使用时钟双边沿逻辑即可完成占空比为 50% 的时钟分频，是最理想的分频状况。</p><p>
奇数分频如果要产生 50% 占空比的分频时钟，则需要使用时钟的双边沿逻辑。如果不要求占空比的话，实现方法和偶数分频类似。</p>
<p>半整数分频属于特殊的小数分频，可以用双边沿逻辑进行设计。通过一定逻辑将两个双边沿时钟信号整合为最后的一路输出时钟时，建议不要使用选择逻辑。因为容易出现毛刺现象，电路中又会增加一定的不确定性。例如下面描述是不建议的。</p>
<div class="example"><div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">assign</span> clk_div3p5 <span style="color: #5D478B;">=</span> <span style="color: #9F79EE;">&#40;</span>cnt <span style="color: #5D478B;">==</span> <span style="color: #ff0055;">1</span> <span style="color: #5D478B;">||</span> cnt <span style="color: #5D478B;">==</span><span style="color: #ff0055;">2</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">?</span> clk_ave_r <br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">:</span> clk_adjust_r <span style="color: #5D478B;">;</span><br />
</div></div>
<p>小数分频的基本思想是，输出时钟在一段时间内的平均频率达到分频要求即可。但是考虑到相位抖动，还需要对分频系数变化的分频逻辑进行平均操作。</p>
<h3>本章节源码下载</h3><p>
<a class="download" href="../wp-content/uploads/2021/05/v5.3_clk_division.zip">Download</a>   </p>				</div>
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		<li>
	5.3 Verilog 时钟分频	</li>
	
		
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	<li><a target="_top" data-id="23813" title="7.2 Verilog 文件操作" href="../w3cnote/verilog2-file.html" >7.2 Verilog 文件操作</a></li>
	
		
	<li><a target="_top" data-id="23825" title="7.3 Verilog 随机数及概率分布" href="../w3cnote/verilog2-random.html" >7.3 Verilog 随机数及概率分布</a></li>
	
		
	<li><a target="_top" data-id="23847" title="7.4 Verilog 实数整数转换" href="../w3cnote/verilog2-real2int.html" >7.4 Verilog 实数整数转换</a></li>
	
		
	<li><a target="_top" data-id="23851" title="7.5 Verilog 其他系统任务" href="../w3cnote/verilog2-other-task.html" >7.5 Verilog 其他系统任务</a></li>
	
		
	<li><a target="_top" data-id="23862" title="8.1 Verilog  PLI 简介" href="../w3cnote/verilog2-pli-intro.html" >8.1 Verilog  PLI 简介</a></li>
	
		
	<li><a target="_top" data-id="23865" title="8.2 Verilog TF 子程序" href="../w3cnote/verilog2-tf.html" >8.2 Verilog TF 子程序</a></li>
	
		
	<li><a target="_top" data-id="23869" title="8.3 Verilog TF 子程序列表" href="../w3cnote/verilog2-tf-sub.html" >8.3 Verilog TF 子程序列表</a></li>
	
		
	<li><a target="_top" data-id="23870" title="8.4 Verilog ACC 子程序" href="../w3cnote/verilog2-acc.html" >8.4 Verilog ACC 子程序</a></li>
	
		
	<li><a target="_top" data-id="23872" title="8.5 Verilog ACC 子程序列表" href="../w3cnote/verilog2-acc-sub.html" >8.5 Verilog ACC 子程序列表</a></li>
	
		
	<li><a target="_top" data-id="23876" title="9.1 Verilog 逻辑综合" href="../w3cnote/verilog2-logic-sumarry.html" >9.1 Verilog 逻辑综合</a></li>
	
		
	<li><a target="_top" data-id="23882" title="9.2 Verilog 可综合性设计" href="../w3cnote/verilog2-integrated-design.html" >9.2 Verilog 可综合性设计</a></li>
	
	</ul></div>	</div>
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